TSMC 0.13 µm CMOS Logic / MS / RF
- Reserve slot
- 25 February 2026
- Final GDS
- 31 May 2026
- Tape-out
- 2 June 2026
- Est. shipment
- 3 August 2026
- Reserve slot → shipment
- 160 days
Source: Europractice 2026 MPW schedule.
FlexMPW
Multi-project wafer manufacturing makes prototype silicon affordable by combining several customer designs into one fabrication run.
But sharing introduces another constraint: everybody has to be ready at the same time.
FlexMPW turns that model around. Projects join continuously, compatible demand accumulates, and xSilica continually computes a manufacturable wafer.
The reality of a shuttle calendar
As one real-world benchmark, the published Europractice TSMC schedule for 2026 contains a single MPW run for TSMC 0.13 µm CMOS Logic / MS / RF. To access it, a team must reserve a shuttle place by 25 February 2026: more than three months before final GDS and five months before shipment. For a team still iterating its product architecture, that is a commitment made long before the design is final.
Source: Europractice 2026 MPW schedule.
FlexMPW principle
~2 week cycle
Manufacturing begins after technical acceptance, not at the next shuttle window.
Conventional MPW solves a real problem: making expensive semiconductor manufacturing accessible to smaller projects.
By grouping designs onto shared production runs, it spreads the cost of a wafer across participants. It works best when a team can plan around a fixed calendar.
The trade-off is timing. If your design is not ready when the window closes, or you decide to change it, you may wait months for the next opportunity.
FlexMPW is built for teams that need the schedule to follow their learning, not the other way around.
Your quantity, your flexibility
A FlexMPW submission defines more than one fixed die quantity. Your preferred quantity is allocated first; you decide how much flexibility xSilica is allowed to use.
If additional quantity has been authorized, the allocation may expand when doing so helps complete the wafer sooner.
Process compatibility
A design may be compatible with more than one Rapid CMOS process configuration. Customers choose which alternatives they are willing to accept.
Accepting more compatible process options increases the number of forming wafers a project can join. A customer who requires one exact configuration can simply restrict the submission accordingly.
More accepted configurations create more paths to silicon.
Illustrative layout
This illustrative layout shows how compatible projects can be allocated on a shared wafer. Actual placement is finalized only when a run closes.
Hover a region to inspect an illustrative allocation. Dicing boundaries and control structures are shown for context.
Platform preview. Run data shown for illustrative purposes only.
Illustrative FlexMPW run
Rapid CMOS · 4-metal · 100 mm
Technical acceptance
Before a project becomes committed, xSilica verifies that it falls within the supported manufacturing and design envelope.
Open FlexMPW runs
Platform preview. Run data shown for illustrative purposes only.
Pilot
Rapid CMOS · 4-metal configuration
68% allocated
7 committed projects · accepting submissions
View runTechnical validation
Rapid CMOS · compatible process options
42% allocated
3 committed projects · accepting submissions
View runPilot
Rapid CMOS · 4-metal configuration
24% allocated
2 committed projects · accepting submissions
View runPayment and closure
Flexible orders fund the maximum quantity authorized. If the final allocation is lower when the wafer closes, the unused amount is refunded.
Ready to reserve manufacturing capacity for your next revision?