From circuit idea to physical silicon
A conventional ASIC project is usually organized around a tape-out. Months of design and verification lead to a single handoff to manufacturing, followed by a long wait for the result.
xSilica is built around a different unit of work: the iterative learning cycle. Design, manufacturing, measurement and customer feedback belong in the same loop, so physical silicon becomes something engineers can learn from repeatedly rather than a one-time endpoint.
In practice, that loop has ten steps.
1. Design
Start with the function you want to learn about in silicon.
A design can combine characterized xSilica components, digital standard cells and transistor-level circuitry, depending on the level of control required. Digital logic can be described at a higher level and mapped onto supported cells, while analog and mixed-signal blocks may be built closer to the device level.
The important constraint is that the design stays inside the supported Rapid CMOS design space. xSilica deliberately supports a narrower process than a general-purpose foundry. That constraint is what allows the design rules, models and manufacturing process to remain tightly aligned.
2. Simulate
Before manufacturing, evaluate how the circuit is expected to behave.
Simulation can answer many questions cheaply: whether logic behaves correctly, whether an analog stage has enough gain, whether a bias point is sensible, or how a circuit responds across the supported operating range.
Simulation is not a substitute for silicon. It is a way to enter manufacturing with a useful hypothesis about what the real device should do.
3. Run technical checks
A design must be manufacturable, not only electrically plausible.
Technical checks verify that the layout and circuit stay within the supported process envelope. These checks cover the physical rules needed by the process, the supported device structures and the manufacturing constraints that make the flow predictable.
The goal is deliberately different from a process that tries to support every possible layout technique. In xSilica, the design space is constrained so that valid designs map cleanly onto the manufacturing process.
4. Choose manufacturing
Once the design is ready, choose how it should enter production.
A Dedicated Wafer gives one project control over the full wafer and is the most direct route when schedule, quantity or process configuration matters most.
A FlexMPW run allows compatible projects to share a wafer. Each project receives its own dies, while flexibility in quantity and placement helps reduce the time needed to assemble a viable shared run.
The circuit does not change between these routes. The choice is primarily about scheduling, allocation and economics. Neither route has to be the eventual high-volume production route; early xSilica wafers can be used to learn before the final manufacturing commitment is made.
5. Manufacture
The design is fabricated using the xSilica Rapid CMOS process.
The process uses a deliberately constrained planar CMOS architecture. The manufacturing sequence still contains the familiar semiconductor building blocks: surface preparation, oxidation, doping, lithography, gate formation, dielectric layers, contacts, metal interconnect and final passivation.
What changes is the operating point. The process, equipment and design rules are selected together for repeatability and short learning cycles rather than for maximum transistor density.
6. Inspect
Manufacturing generates more information than a finished wafer alone.
Dedicated control structures and optical inspection are used to assess process health and physical pattern quality. They help distinguish obvious manufacturing problems from questions that can only be answered electrically.
Inspection can reveal missing or damaged structures, alignment errors and visible pattern defects. Electrical test structures provide the complementary information needed to understand device behavior.
7. Dice
Where required, the completed wafer is separated into individual dies.
Dicing sounds like a simple backend operation, but it determines how the silicon can be handled and used next. A project intended for wafer probing may not need every die separated immediately. A project going into a carrier or package usually does.
8. Receive
The result can be delivered in the backend form that best matches the next engineering question.
For the fastest laboratory evaluation, that may be bare die. For easier electrical access, an evaluation carrier may be more practical. Where a prototype needs to behave like a normal PCB component, a conventional package can be appropriate.
Packaging is therefore not automatically the final step. It is another engineering choice inside the development loop.
9. Measure
Measurement is where the model meets reality. Compare the electrical behavior of the manufactured device with the assumptions made during design. For a digital block, that may mean verifying logic, timing and interfaces. For an analog circuit, it may mean tracing transfer characteristics, gain, offsets, leakage, bias points or temperature behavior.
A measurement tells you more than whether the circuit worked. It shows which assumptions held up, which did not and where the model or the design needs to improve.
10. Feedback & Improve
Put the silicon into the product where that is useful, get it in front of early adopters, and combine their feedback with what the measurements taught you.
The next revision might correct a mistake, change a circuit parameter, select a better architecture, add observability, tighten a model or try two competing solutions side by side.
The first revision does not need to be perfect. It needs to teach you enough to make the second one better, and the interval between them needs to be short enough that silicon itself can become part of the engineering method.