The ASIC decision is not determined by volume alone
The conventional ASIC decision is often reduced to one question:
Are the volumes high enough to justify the investment in a mask set?
There is a sound economic reason for that rule. A conventional ASIC programme converts a large amount of development effort into fixed, product-specific non-recurring engineering cost, or NRE. Once that investment has been made, a custom chip can become very inexpensive per unit. The traditional business case is therefore a break-even calculation: invest upfront, then recover that investment through lower recurring cost over enough production volume.
The mask set is the most visible part of that commitment, but it is not the whole commitment. Published ASIC cost analyses separate NRE into engineering labour, EDA tools, IP, package design and tooling, verification, qualification and masks. A 2019 industry analysis goes further and notes that IP, development and qualification can amount to several times the mask-set NRE REF1. An academic NRE model reaches the same broader conclusion: at older nodes, labour, CAD, IP and packaging can outweigh the masks themselves REF2.
That distinction matters because simply finding cheaper wafer access does not make the complete ASIC programme cheap. The question is how much irreversible cost has to be committed before the design, and sometimes the product itself, has finished learning.
The conventional calculation works well when the product is already understood
Published examples show the traditional model clearly.
One anonymized 130 nm automotive ASIC case from late 2016 replaced an MCU and several analog components. The reported ASIC design and mask NRE was about $1 million, with another $392,000 for automotive qualification and productization. At 40,000 to 45,000 units per month and an ASIC unit price of $1.46, the investment reached payback in less than nine months REF1.
A more recent worked example from Presto Engineering uses a $4 million upfront ASIC investment, a $4 ASIC unit cost and a $10 discrete implementation at 500,000 units per year. In that simplified model, the $6 saving per unit produces $3 million in annual savings and pays back the initial investment in roughly 18 months REF3.
These examples are not price quotations for a new xSilica customer, nor are they directly comparable with one another. They illustrate the conventional economic mechanism: large fixed NRE becomes rational when the product is stable enough and the recurring volume is high enough to recover it.
The interesting cases for rapid silicon are the ones where that conventional calculation breaks down.
1. Your volume is too low for traditional ASIC economics
Some products will never ship in millions. Industrial instruments, specialist sensors, laboratory systems, aerospace electronics and other high-value products may need only thousands or tens of thousands of devices per year.
At that scale, fixed NRE dominates the equation. Saving several euros on each manufactured chip has limited value if the programme requires hundreds of thousands or millions in upfront engineering before the first useful unit exists. Swindon Silicon Systems makes the same lifecycle distinction in its ASIC-versus-FPGA guidance: products in the hundreds or low thousands often favour programmable hardware, while the economics begin to shift toward ASIC as volume rises REF5.
That does not mean custom silicon is technically unnecessary. The integrated solution may still be smaller, lower power, easier to protect, easier to source or better matched to the sensing problem. The barrier is that the fixed commitment is too large relative to the number of products over which it can be recovered.
Lowering that fixed commitment moves the threshold. The relevant question becomes less about annual units and more about how much system value integration creates compared with the cost of reaching useful silicon.
2. Time matters more than unit price
For many development programmes, the expensive part is not the silicon. It is waiting.
A multidisciplinary engineering team continues to consume budget while a project is waiting for a manufacturing slot, a shuttle deadline or the return of first silicon. If a design cycle takes several months, the indirect cost can exceed the price of another prototype run. Teams naturally find other useful work while they wait, but feedback is most valuable while the architecture decisions, simulation results and unresolved corner cases are still fresh.
This matters particularly in industrial R&D, defense, aerospace, specialized instrumentation and other programmes where schedule has strategic value. In those cases, paying more per prototype die can be economically sensible if it resolves an architectural question months earlier.
The useful comparison is therefore not simply:
What does one die cost?
It is:
What does one learning cycle cost, including the engineering time between design decisions?
3. The product is not mature yet
Traditional ASIC advice usually says to wait until the product architecture is stable. That advice is rational when each silicon revision carries a large financial and calendar penalty.
Industry sources explicitly recognize requirements maturity as part of the go/no-go decision. In a 2016 imec IC-Link article based on interviews with Easics, ICsense and Sofics, the decision for a startup or innovative SME was described as being dominated by upfront NRE, time-to-market and the ability to define the chip requirements precisely REF4. A current imec overview still describes ASIC development as a chain that begins with stable product requirements and continues through architecture, verification, packaging, manufacturing, test and qualification REF6.
The problem is that some important product questions are hard to answer without integration. Power consumption can change when functions move on-chip. Sensor performance can depend on the analog front-end. A required form factor may simply be impossible with individually packaged catalog components. Timing, signal integrity, security and copy protection can also change materially once board-level interconnect and standard components disappear.
If silicon is introduced only after those questions are supposedly settled, the team has to settle them without the prototype medium that could answer them best.
For an early-stage product, this suggests another useful concept: NRE at risk.
A break-even calculation normally assumes that the product launches, the architecture is correct and the forecast volume materializes. Before product-market fit, all three assumptions may still be uncertain. The less mature the product, the more valuable reversible engineering decisions become, because money committed to a product-specific implementation may never be recovered if the product changes direction or is stopped entirely.
A shorter silicon cycle changes the strategy. Revision A0 can answer a limited set of questions rather than encode the entire final product. Revision A1 can incorporate what was learned. Custom silicon then moves earlier into the development curve, where it can help determine the architecture rather than merely implement an architecture that has already been frozen.
Sometimes the ASIC is valuable even before it is cheaper
Unit-cost break-even is not the only reason to integrate.
The second real-world case in the 2019 industry analysis concerned a medical telemetry product. The discrete implementation was estimated at $7.56 per unit, while the proposed 65 nm ASIC carried $5.3 million of NRE and a $2.30 unit price, leading to a break-even around one million units. Yet the discrete implementation also fell outside the required power budget. The ASIC was not simply a cheaper version of an otherwise adequate architecture; it enabled a product requirement the catalog-component solution could not meet REF1.
This distinction is particularly important in mixed-signal products. A custom analog front-end, sensor interface, timing function or power-sensitive signal chain can change what the product is physically capable of doing. ICsense makes the same point in its PCB-to-custom-IC material, framing the migration in terms of cost, size, performance, power, supply and other business and technical factors rather than unit price alone REF7.
A better way to frame the decision
For an iterative product, the ASIC decision should combine five questions:
- What system constraint would integration remove? Power, size, component count, sensing performance, security, supply-chain dependence or something else?
- How much fixed NRE is being committed before the product is stable? Include design, tools, IP, package and qualification, not just masks.
- What does waiting cost the programme? Include engineering time and delayed decisions, not only wafer cost.
- Which uncertainties can only be resolved in silicon? Those are candidates for an early prototype rather than another month of abstract analysis.
- What happens after the architecture stabilizes? Rapid prototyping and high-volume production do not have to use the same manufacturing route.
Rapid silicon is not a claim that every product should remain on a micron-scale process forever. Once the design is stable and volume economics dominate, a conventional production process may be the right answer.
The change is that the ASIC decision no longer has to wait for that moment. Conventional ASIC economics optimize the cost of the finished product. An iterative silicon model also optimizes the cost and time of learning what the finished product should be.
References
[1] I. Lankshear, “The Economics of ASICs: At What Point Does a Custom SoC Become Viable?,” Electronic Design, Jul. 15, 2019. [Online]. Available: https://www.electronicdesign.com/technologies/embedded/article/21808278/ensilica-the-economics-of-asics-at-what-point-does-a-custom-soc-become-viable. [Accessed: Sep. 8, 2026].
[2] M. Khazraee, L. Zhang, L. Vega, and M. B. Taylor, “Moonwalk: NRE Optimization in ASIC Clouds,” in Proc. 22nd ACM Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS), Xi'an, China, 2017, pp. 511–526, doi: 10.1145/3037697.3037749. [Online]. Available: https://michaeltaylor.org/papers/Khazraee_ASIC_Cloud_NRE_ASPLOS_2017_final.pdf.
[3] Presto Engineering, “ASIC vs Discrete Solution: Why Custom Chips Win in the Long Run,” Mar. 26, 2025. [Online]. Available: https://www.presto-eng.com/articles/asicvsdiscretesolution. [Accessed: Sep. 8, 2026].
[4] imec, “Innovate with hardware in today’s substream markets,” Dec. 23, 2016. [Online]. Available: https://www.imec-int.com/en/articles/the-new-hardware-hipsters. [Accessed: Sep. 8, 2026].
[5] Swindon Silicon Systems, “ASIC vs FPGA: How to Choose the Right Architecture for Real-World Products,” Jun. 28, 2026. [Online]. Available: https://www.swindonsilicon.com/asic-vs-fpga-how-to-choose-the-right-architecture/. [Accessed: Sep. 8, 2026].
[6] imec, “When does an ASIC make sense for your product?,” Jan. 28, 2026. [Online]. Available: https://www.imec-int.com/en/articles/when-does-asic-make-sense-your-product. [Accessed: Sep. 8, 2026].
[7] ICsense, “Going from PCB to a custom IC.” [Online]. Available: https://www.icsense.com/going-from-pcb-to-a-custom-ic/. [Accessed: Sep. 8, 2026].