Shared manufacturing needs synchronization
Multi-project wafers made prototype silicon dramatically more accessible. Instead of paying for an entire mask set and wafer run, multiple customers place independent designs on the same manufacturing lot and share the fixed cost. Europractice states that this can reduce the fabrication cost of a prototype run to roughly 5% to 10% of the cost of a dedicated prototyping wafer REF2.
The trade-off is time, and not primarily because a wafer spends months inside process equipment. A significant part of the elapsed calendar comes from everything required to make shared manufacturing efficient.
A shuttle is a coordinated batch
A conventional MPW run usually follows a sequence like this:
- A foundry or intermediary publishes a shuttle opportunity.
- Customers reserve space and prepare their designs for that process well in advance.
- Designs pass the required technical and administrative checks.
- Everyone works toward the same commitment and tape-out deadline.
- The individual designs are assembled into one shared mask and wafer plan.
- The shared lot enters the fab schedule.
- Wafers move through fabrication, test and any agreed backend steps.
- The resulting dies are separated and distributed to the individual customers.
None of these steps is unusual on its own. The delay appears because many independent projects have to be synchronized around the same manufacturing event.
A design that is ready early cannot necessarily start early because the shared run is not ready. A design that misses the commitment date cannot simply join a mask set that has already closed. The development calendar therefore follows the shuttle, not the readiness of one individual project.
Batching is what makes MPW affordable
This is the central economic trade-off in MPW: it is affordable because many projects agree to share the same manufacturing setup.
The same mechanism that shares mask and wafer cost also creates the queue. The provider needs enough compatible designs to make the shared run economical, and the fab needs to insert that lot into a production environment optimized for expensive equipment and high utilization.
If every small prototype project demanded immediate access, the economics would begin to resemble dedicated manufacturing rather than MPW. The calendar is therefore not an accidental inconvenience added to the service. It is part of the cost-sharing mechanism.
The fab is optimized for utilization, not for your next learning cycle
Conventional semiconductor fabs are capital-intensive systems. Their economics reward keeping equipment productive, grouping compatible work and minimizing disruption to the main production flow. That is exactly the right objective for high-volume manufacturing, but it is different from minimizing the time between two prototype revisions for one engineering team.
The prototype customer cares about a short loop: design, build, measure, improve. The fab cares about moving many lots efficiently through shared equipment. Both objectives are rational; they simply optimize different things.
A real 2026 shuttle calendar
The TSMC 0.13 µm CMOS Logic/MS/RF entry in Europractice's March 17, 2026 schedule is a useful reality check REF1.
| Published milestone | Date |
|---|---|
| Reserve slot before | 25 February 2026 |
| Signed quotation / PO before | 3 April 2026 |
| Dry-run GDS | 6 May 2026 |
| Final GDS | 31 May 2026 |
| Tape-out | 2 June 2026 |
| Estimated shipment | 3 August 2026 |
Because the first date explicitly says reserve before, a customer must commit no later than 25 February. From that reservation deadline to the estimated shipment date is about 160 calendar days. Only the final part of that window occurs after tape-out.
The schedule also notes that the shipment date is an estimate and that additional cycle time of one to three weeks may be required in some circumstances REF1.

The frequency of the shuttle can matter as much as the node
The same schedule contains another revealing detail. It lists one general 0.13 µm Logic/MS/RF run in 2026, while the 65 nm Logic/MS/RF process has seven listed runs REF1.
That means the apparently more mature process is not automatically the faster development platform. A team that discovers an issue after the only 130 nm shuttle may wait far longer for the next opportunity than a team working on a process with a denser shuttle calendar.
This introduces a variable that is easy to miss when comparing process nodes:
How soon can the next revision actually enter manufacturing?
A process can be attractive on die cost, analog capability or mask economics and still be a poor choice for iterative development if the next available shuttle is months away.
Fabrication time is only one clock
When people hear a four- or six-month MPW lead time, it is tempting to assume that fabrication itself takes that long. The published schedule shows why that interpretation is incomplete.
The total calendar includes several different forms of waiting:
- time between reservation and final design submission
- technical and administrative preparation
- time until the shared mask set closes
- queueing before and inside the fab
- the actual sequence of fabrication steps
- wafer test, dicing and backend processing
- distribution of each customer's dies
A faster design tool can shorten the first part of the job, but it cannot remove a fixed manufacturing calendar. If the design finishes three weeks earlier, it simply reaches the same shuttle deadline three weeks earlier.
Why xSilica starts somewhere else
xSilica is not trying to make a conventional high-volume fab behave like a prototype shop. The manufacturing system starts from a different objective: shorten the design-to-measurement loop.
That is why the process is deliberately constrained, why the equipment architecture is compact, and why FlexMPW uses continuous matching rather than a fixed shuttle calendar. Traditional MPW is an effective way to share access to expensive manufacturing infrastructure. xSilica asks what the manufacturing system should look like when iteration speed itself becomes the primary design constraint.
References
[1] EUROPRACTICE IC Service, “TSMC Run Schedule 2026,” ver. 1.4, Mar. 17, 2026. [Online]. Available: https://europractice-ic.com/wp-content/uploads/2025/11/TSMC_EP_MPW_schedule2026_v1_4.pdf. [Accessed: Sep. 8, 2026].
[2] EUROPRACTICE, “MPW Fabrication.” [Online]. Available: https://europractice-ic.com/services/fabrication/. [Accessed: Sep. 8, 2026].