Packaging is another engineering decision
A finished wafer is not automatically a finished component. Before a chip can be handled like a normal part on a PCB, the individual die usually needs some form of backend processing: dicing, mechanical protection, electrical connection and sometimes a complete package.
For rapid prototyping, the best backend is the one that answers the next engineering question without adding unnecessary time or complexity.
Bare die
Bare die is the shortest path from wafer to measurement.
After dicing, the silicon can be handled directly and connected through probing, a laboratory fixture, wire bonding or a chip-on-board experiment.
Bare die is attractive when the immediate objective is electrical characterization. It avoids the extra lead time and cost of a production-style package and keeps physical access to the device straightforward.
Typical uses include:
- wafer or die probing
- parameter characterization
- early bring-up
- chip-on-board experiments
- destructive or exploratory testing
The trade-off is practical handling: bare silicon is mechanically fragile and less convenient to integrate into a normal development PCB.
Evaluation carrier
An evaluation carrier sits between bare die and a production package.
The die is mounted onto a reusable or semi-standard substrate that brings the bond pads out to connectors, larger pads or a PCB-friendly interface. The objective is not necessarily to reproduce the final product package. It is to make the prototype easier to power, probe and connect.
This can be a useful default for engineering work because the silicon remains accessible while the test setup becomes much more practical.
An evaluation carrier is especially useful when several revisions of the same die will be compared using the same laboratory hardware.
QFN
A QFN package makes the prototype behave much more like a conventional electronic component.
That can be valuable once the engineering question moves from “does the silicon work?” to “does the silicon work inside the system?”
A packaged part is easier to assemble onto a PCB, easier to exchange between teams and better suited to realistic integration tests.
The trade-off is that packaging adds operations, cost and lead time. Wire bonding, package assembly and final handling become part of the backend flow.
For an early device-characterization revision, that may be unnecessary overhead. For a system prototype that needs to go into a product enclosure, it may be exactly the right choice.
WLCSP
Wafer-level chip-scale packaging takes a different approach.
Rather than placing each die into a separate molded package, electrical redistribution and external connections are created at wafer level before the dies are separated. The result can be extremely compact and close to the dimensions of the silicon itself.
That makes WLCSP attractive for space-constrained products, but it is not simply “dicing with solder balls added”. It requires additional qualified backend processes and design rules.
For xSilica, wafer-level packaging is therefore a backend option to qualify deliberately as the platform matures, not something that should be assumed for every early prototype.
Prototype packaging is not the same as productization
There is another distinction worth keeping clear: putting a prototype die into a package is not the same as turning the IC into a qualified production component.
A current imec ASIC lifecycle overview treats package design, assembly, testing and final qualification as separate parts of the journey from architecture to mass production REF1. The Moonwalk NRE model likewise treats package design and tooling as a separate non-recurring cost rather than part of the wafer price REF2.
For a prototype, the goal is usually much narrower. You may only need reliable electrical access so the next engineering question can be answered. Qualification, production test coverage, long-term package reliability and manufacturing scale can come later, once the silicon and product architecture have earned that investment.
Choose the backend that answers the next question
There is no universal packaging hierarchy in which more packaging is always better. A useful way to decide is:
| Next engineering question | Likely backend |
|---|---|
| What are the electrical characteristics of the device? | Bare die or wafer probe |
| Can I connect the die conveniently on the bench? | Evaluation carrier |
| Does it work in a realistic PCB and system? | QFN or another conventional package |
| Does the final product require minimum package size? | Consider WLCSP once qualified |
The fastest silicon loop comes from doing only the backend work needed for the next decision. Packaging should therefore be chosen as part of the experiment, not treated as an automatic final step after fabrication.
References
[1] imec, “When does an ASIC make sense for your product?,” Jan. 28, 2026. [Online]. Available: https://www.imec-int.com/en/articles/when-does-asic-make-sense-your-product. [Accessed: Sep. 8, 2026].
[2] M. Khazraee, L. Zhang, L. Vega, and M. B. Taylor, “Moonwalk: NRE Optimization in ASIC Clouds,” in Proc. 22nd ACM Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS), Xi'an, China, 2017, pp. 511–526, doi: 10.1145/3037697.3037749. [Online]. Available: https://michaeltaylor.org/papers/Khazraee_ASIC_Cloud_NRE_ASPLOS_2017_final.pdf.