Revision one does not need to be the final product
The expected time to the next revision changes how engineers design the current one. If a silicon respin takes six months and consumes a major budget, the natural strategy is defensive: resolve every uncertainty you can, verify for as long as possible, avoid experimental ideas and optimize the design before the first wafer exists.
That mindset is not irrational. A conventional ASIC economics article summarizes it with the familiar advice to “measure twice, cut once” because a specification mistake is expensive to correct after tape-out REF1. Current ASIC-versus-FPGA guidance makes the same lifecycle point from another direction: when the specification is still changing, programmable logic reduces the cost and schedule risk of architectural changes REF2.
If a new silicon revision can arrive in weeks, the strategy can change without abandoning good engineering discipline. The silicon can be designed to produce information, not only to be correct.
Decide what belongs in silicon now
Before deciding how to instrument revision A0, decide which parts of the product should be frozen into A0 at all.
This matters particularly in mixed-signal systems. Some functions gain their value specifically from physical integration: an analog front-end close to a sensor, a low-noise interface, a compact timing circuit, a data converter, or another block whose power, size or signal quality is difficult to achieve from catalog components. Other functions may still be changing rapidly because the team is learning about customer behaviour, algorithms, protocols or the product architecture.
There is no rule saying both groups have to be frozen at the same time.
A useful early architecture may therefore place the physics-bound functions in custom silicon while keeping fast-moving digital behaviour in an FPGA or external microcontroller. ICsense describes the PCB-to-custom-IC transition in exactly this broader system context, where cost, size, performance, power and supply considerations are evaluated together rather than treating the ASIC as an all-or-nothing replacement for the board REF3. Imec's earlier work with ASIC design partners similarly identifies requirements maturity as one of the dominant go/no-go factors for innovative companies REF4.
The design principle is simple: do not commit an uncertain function to silicon merely because it will eventually belong there.
For example, an early mixed-signal prototype might integrate:
- the sensor interface
- analog filtering or amplification
- ADC or DAC functions
- clocking and timing
- circuitry whose form factor or power depends on integration
while leaving these outside the die for another revision:
- algorithms still changing weekly
- DSP architecture under active development
- application state machines
- protocol behaviour
- customer-facing features that may disappear entirely
Once those functions stabilize, they can move on-chip in a later revision. This keeps the first silicon focused on the questions that genuinely require silicon.
Start with the question the revision must answer
Before tape-out, write down what you expect to learn from the silicon. “Prove the chip works” is too broad; a useful learning objective is more specific:
- Which architecture choice are we uncertain about?
- Which device parameter matters most to system performance?
- Which simulation assumption do we need to validate?
- Which interface is most likely to create trouble?
- What measurement would change the next design decision?
A revision with a clear learning objective is much easier to instrument. Several design techniques make that possible.
Observability
Expose important internal signals where practical.
A node that exists only inside the die may be impossible to diagnose once the circuit is fabricated. Bringing selected internal signals to pads, test multiplexers or dedicated observation points can make a failed block understandable instead of mysterious.
Observability costs area and I/O, but in an early prototype that cost can be far smaller than the cost of not knowing what went wrong. If the intended package offers fewer pins than characterization requires, use an evaluation carrier or bare die for the early revision so the necessary signals remain accessible. Once the behavior is understood, later revisions can remove those test connections and return to the intended user-facing pin count.
Test modes
Allow internal functions to be isolated or controlled directly.
A normal operating mode may connect several blocks into one closed system. If the output is wrong, it can be difficult to determine which block caused the problem.
Test modes can bypass part of the signal chain, force a known state, inject a controlled stimulus or operate one subsystem independently.
That turns one complicated failure into several smaller experiments.
Trim options
Parameters that are uncertain do not always need to be fixed permanently in the first revision.
Add trim options where small parameter changes may recover useful behavior or reveal the correct design point. This can be done with selectable device segments, resistor options, digital control bits or other structures appropriate to the circuit.
The purpose of trimming in a prototype is not necessarily production calibration. It can simply be a way to sweep the physical design space after fabrication.
Where the circuit allows it, an internal node can also be routed to a pad so that a precision resistor or capacitor remains external during early characterization. That could be an analog filter capacitor, a bias resistor for a current mirror or another value that is still uncertain. SMT passives are much easier to change than on-chip structures, so this can postpone a sensitive design decision until measurements have narrowed the useful range.
Configuration
Where an architectural choice is uncertain, make it selectable.
A prototype can contain multiple operating modes, selectable signal paths, alternative device sizing or programmable settings that would be unnecessary in the final product. One piece of silicon can then test several assumptions, and later revisions can remove that flexibility once the preferred configuration is known.
Experimental blocks
If two small implementations could plausibly solve the same problem, it may be more efficient to fabricate both than to spend weeks trying to predict which one will win.
Experimental blocks are especially useful for analog structures, device geometries, interfaces and process-sensitive circuits where real silicon contains information that simulation cannot provide perfectly. Keep the alternatives isolated enough that they can be measured independently.
Process monitors
Include structures that help separate process behavior from circuit behavior.
Simple transistors, resistive structures, contacts or other reference elements can provide a baseline for interpreting the customer circuit.
If the circuit changes and the process monitor changes with it, the investigation takes a different path than when the monitor remains stable. Including relevant test structures alongside the circuit also gives you measured device data that can be compared with the assumptions used in simulation. That is one of the important differences between merely receiving silicon and learning from it.
Redundancy
Where area permits, duplicate critical or experimental functions.
Redundancy can be used in several ways:
- repeat the same structure to see whether behavior is consistent
- place variants with one parameter changed
- create a fallback implementation
- distribute structures to reveal location-dependent process effects
In a production ASIC, duplicated circuitry may look wasteful. In a learning vehicle, it can be cheap insurance.
Do not optimize away the experiment
A conventional tape-out culture rewards completeness before manufacturing and efficiency inside the die.
Rapid iteration rewards something different: the amount of uncertainty removed per cycle.
That does not mean replacing verification with trial and error. Simulation, DRC, verification and design review are still cheaper than fabricating avoidable mistakes. The difference is that not every uncertainty has to be eliminated analytically before tape-out. When physical measurement is the fastest reliable way to answer a question, the silicon can be designed so that the question is measurable.
That may mean accepting a larger die, extra pads, duplicated blocks or configuration logic in an early revision. Those features can disappear later, after they have done their job.
An early revision does not need to be elegant if the extra circuitry makes it substantially more informative.
Make revisions comparable
Fast iteration becomes much more powerful when each run produces data that can be compared with the previous one.
Keep measurement methods stable where possible. Record the configuration of each test structure. Preserve reference blocks between revisions. Change one important variable at a time when the goal is to understand cause and effect.
That turns a sequence of prototype wafers into a growing body of engineering evidence.
Design silicon the way strong teams design prototypes
A good PCB prototype is rarely a miniature production board with every uncertainty optimized away. It often contains test points, jumpers, spare footprints, alternate components and measurement access because the engineer expects to learn from it.
Rapid silicon can be approached with the same mindset: build enough to answer the next set of questions, measure it carefully, and use the result to decide what belongs in the next revision.
References
[1] I. Lankshear, “The Economics of ASICs: At What Point Does a Custom SoC Become Viable?,” Electronic Design, Jul. 15, 2019. [Online]. Available: https://www.electronicdesign.com/technologies/embedded/article/21808278/ensilica-the-economics-of-asics-at-what-point-does-a-custom-soc-become-viable. [Accessed: Sep. 8, 2026].
[2] Swindon Silicon Systems, “ASIC vs FPGA: How to Choose the Right Architecture for Real-World Products,” Jun. 28, 2026. [Online]. Available: https://www.swindonsilicon.com/asic-vs-fpga-how-to-choose-the-right-architecture/. [Accessed: Sep. 8, 2026].
[3] ICsense, “Going from PCB to a custom IC.” [Online]. Available: https://www.icsense.com/going-from-pcb-to-a-custom-ic/. [Accessed: Sep. 8, 2026].
[4] imec, “Innovate with hardware in today’s substream markets,” Dec. 23, 2016. [Online]. Available: https://www.imec-int.com/en/articles/the-new-hardware-hipsters. [Accessed: Sep. 8, 2026].