Geometry is an engineering choice, not a measure of technological seriousness
For more than fifty years, the semiconductor industry has used smaller feature sizes as the most visible measure of progress.
That focus is justified for many products. Shrinking transistors enabled extraordinary increases in computing performance, memory density and energy efficiency. A processor, accelerator or large memory may have no practical alternative to a modern dense process.
But node selection is still an engineering decision, not a ranking of how advanced a product is.
A useful academic example comes from Moonwalk: NRE Optimization in ASIC Clouds. The authors modelled ASIC implementations across nodes from 250 nm to 16 nm and treated the process node as an economic design variable rather than automatically choosing the newest technology. Their conclusion was not that old silicon is always better. It was that the optimal node depends on the workload, required performance, transistor count and the NRE that has to be recovered REF1.
That principle is directly relevant to xSilica: first determine what the function actually requires, then choose the manufacturing geometry that best serves that objective.
Critical dimension affects the entire manufacturing system
As the critical dimension becomes smaller, more than the lithography tool changes.
Pattern placement, film thickness, etch control, contamination, metrology and alignment all have to operate inside tighter process windows. Advanced processes therefore depend on increasingly capable equipment and increasingly controlled factory infrastructure. That capability is valuable when the product needs the resulting density and performance, but it also raises the cost and complexity of developing and operating the manufacturing system.
Once that capital has been installed, the economic objective of the fab follows naturally: keep expensive equipment utilized, process large wafer volumes and minimize disruption to a tightly controlled production flow.
xSilica deliberately chooses a different operating point. Rapid CMOS uses micron-scale geometry, far from the leading edge, because the platform is optimized for short and controllable design-to-silicon cycles rather than maximum transistor density.
The important claim is not that “large transistors are cheap.” The point is that a larger process window gives us more freedom to simplify the whole manufacturing architecture around the application.
Larger geometry creates process margin
At micron-scale dimensions, features are larger, alignment tolerances can be more conservative, and lithography does not need to operate close to the resolution limits that dominate advanced-node manufacturing. Design rules can be easier to understand and inspect, while the required equipment can be simpler and more compact.
That larger process window supports several choices that are central to xSilica:
- simpler lithography
- larger alignment and dimensional margins
- reduced equipment complexity
- conservative design rules
- easier optical inspection and metrology
- lower capital intensity per manufacturing cell
- faster process development and troubleshooting
None of this makes semiconductor manufacturing trivial. Oxide quality, contamination, diffusion profiles, interface states, contact resistance, film quality and repeatability still determine whether the devices work.
Micron-scale geometry does not remove semiconductor physics. It gives the engineering team a less hostile process envelope in which to control it.
Smaller is not automatically better for every function
A leading-edge node is invaluable when the product needs enormous transistor density, very high digital performance or large on-chip memories. Many control and sensing functions do not.
State machines, sensor interfaces, comparators, oscillators, bias circuits, modest data converters and mixed-signal control can create substantial system value without billions of transistors. For those functions, the critical constraint may instead be:
- putting the electronics into a smaller physical location
- reducing discrete component count
- placing an analog front-end close to a sensor
- integrating product-specific control
- protecting a function inside custom hardware
- learning quickly enough to improve the product architecture
If density is not the limiting requirement, there is little reason to inherit every complexity that comes with maximizing it.
Mixed-signal does not scale like digital
The distinction becomes particularly important for analog and mixed-signal circuitry.
Digital logic benefits strongly from smaller transistors because more gates fit into the same area and switching performance can improve. Analog circuits often behave differently. Capacitors are sized by capacitance, noise and matching requirements; resistors consume physical area; and analog transistors are frequently made deliberately larger than the minimum geometry to improve noise or matching.
In a 2016 imec IC-Link discussion, ICsense explicitly argued that analog interface circuits often gain little area from moving to deep-submicron nodes and can become harder to design as supply voltage and dynamic range fall. The article cited 0.18 µm as a typical preferred node for analog interface applications at that time REF2. Swindon Silicon Systems makes the same broader distinction in current guidance, noting that mixed-signal ASICs integrate analog signal conditioning in ways an FPGA cannot and that the appropriate CMOS node depends on the application's power, signal and performance requirements REF3.
That does not prove that every analog product belongs on a large node. It shows why “smaller is better” is particularly weak as a universal rule for mixed-signal systems.
Mature geometry alone does not solve ASIC accessibility
There is an equally important lesson in the Moonwalk study. Moving to an older node reduced mask and some IP costs sharply, but frontend labour changed little and tool, package and other engineering costs remained significant. In the authors' NRE breakdown, non-mask costs could dominate at older nodes REF1.
That is a useful warning for xSilica.
Simply choosing an old process node does not automatically create an accessible custom-silicon platform. If the design still requires a specialist toolchain, if verification still carries the same burden, and if manufacturing still runs through the same batch-oriented infrastructure, much of the conventional NRE remains.
This is why xSilica co-designs three layers together:
- the fabrication process
- the design environment
- the manufacturing equipment and control system
The geometry is an enabler of that simplification, not the entire proposition.
Why xSilica goes beyond conventional mature nodes
The academic work above studied conventional nodes down to 250 nm. It does not validate xSilica's choice of a 1 to 10 µm process, and we should not pretend that it does.
What it validates is the more general principle that the newest available node is not automatically the economically optimal node. xSilica takes that principle much further because the objective is different again: we are not trying to find the cheapest conventional foundry node for a finished ASIC. We are designing a process and manufacturing cell around iteration speed, controllability and low fixed commitment.
That is why features substantially larger than mainstream mature nodes can still be a rational engineering choice, provided the required function fits.
Mature physics, modern engineering
The underlying device structures are classical CMOS. The way they are developed and operated does not have to be classical.
Modern motion control, machine vision, software orchestration, simulation, automated measurement and data analysis can be applied to a process whose physical dimensions are intentionally forgiving. The result is not an attempt to reproduce a 1970s fab. It is an attempt to apply modern engineering methods to a part of CMOS physics where the density race is no longer the objective.
References
[1] M. Khazraee, L. Zhang, L. Vega, and M. B. Taylor, “Moonwalk: NRE Optimization in ASIC Clouds,” in Proc. 22nd ACM Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS), Xi'an, China, 2017, pp. 511–526, doi: 10.1145/3037697.3037749. [Online]. Available: https://michaeltaylor.org/papers/Khazraee_ASIC_Cloud_NRE_ASPLOS_2017_final.pdf.
[2] imec, “Innovate with hardware in today’s substream markets,” Dec. 23, 2016. [Online]. Available: https://www.imec-int.com/en/articles/the-new-hardware-hipsters. [Accessed: Sep. 8, 2026].
[3] Swindon Silicon Systems, “ASIC vs FPGA: How to Choose the Right Architecture for Real-World Products,” Jun. 28, 2026. [Online]. Available: https://www.swindonsilicon.com/asic-vs-fpga-how-to-choose-the-right-architecture/. [Accessed: Sep. 8, 2026].