Start with the function, not the transistor count
The obvious question about a micron-scale process is density: if modern processors contain billions of transistors, how useful can a chip be when its features are measured in micrometres?
It is a reasonable comparison, but usually the wrong starting point.
Density still matters, but it is better treated as a constraint than as the objective. In the Moonwalk node-selection study, older nodes are filtered out when they cannot satisfy the required transistor count, frequency or latency. Only among the nodes that can actually perform the job does the economic optimization begin REF1.
That is a useful way to think about Rapid CMOS as well: first ask whether the required function fits and meets its electrical requirements; only then ask whether a smaller node would be preferable.
Most application-specific chips are not trying to become processors. They are trying to implement either a mixed-signal design, or one valuable function in a better place, with a better interface, at lower system complexity or with tighter integration than a PCB full of catalog components can provide.
Useful digital logic can be small
Many digital functions need surprisingly little logic compared with a general-purpose computer.
Examples include:
- state machines
- counters and timers
- PWM generation
- sequencing and supervisory logic
- simple communication interfaces
- protocol adaptation
- control loops implemented in digital logic
- application-specific glue logic
These circuits do not need caches, operating systems, graphics engines or large memories. They implement a narrow function repeatedly and deterministically, which is precisely where custom silicon can be useful.
Once the xSilica standard-cell library is characterized, digital designs can be synthesized into a known set of gates and physical cells. The relevant density will then be measured from real layouts and real silicon rather than estimated from a nominal feature size alone.
Analog value does not scale with transistor count
Transistor count is an even weaker proxy for analog usefulness.
Analog circuits often scale much less directly with minimum feature size than digital logic. Capacitors, resistors, matching structures and low-noise devices may retain substantial physical dimensions even when the process node shrinks. A 2016 imec IC-Link discussion with ICsense makes this point explicitly for analog interface circuits REF2.
A comparator may use a small number of devices but answer a system-critical question. An operational amplifier can replace a cluster of discrete components. A bias circuit, oscillator or sensor interface may enable an architecture that is difficult to reproduce cleanly at board level.
Typical mixed-signal building blocks within the intended xSilica design space include:
- comparators
- bias and reference circuits
- operational amplifiers
- oscillators
- sensor interfaces
- analog front-ends
- moderate-complexity ADC and DAC structures
The value of those blocks comes from where they are integrated and what system function they enable, not from how many transistors they contain.
Die area is shared by more than transistors
A real IC is not a rectangle filled uniformly with logic.
Area is also consumed by routing, analog devices, isolation, contacts, power distribution, test structures and external connections. A process with a limited number of metal layers must use that routing resource deliberately. Analog structures may be intentionally large to obtain a useful electrical characteristic or matching behavior.
This means two circuits with the same transistor count can have very different physical sizes.
A useful capacity estimate therefore has to consider the actual design, not only a theoretical transistor density.
The practical question is whether the function fits economically
For Rapid CMOS, the useful question is not how many billions of transistors fit on the wafer. It is whether the required function can fit on a die whose size and manufacturing cost make sense for this development programme.
That framing leads to more useful engineering questions: what must be integrated, which functions can remain external, how much analog area is required, how many I/O connections are needed, whether dense memory is actually necessary, and whether two smaller experimental blocks would teach more than one heavily optimized implementation.
Those decisions determine whether the function fits economically far more directly than a headline node comparison does.
xSilica will publish measured capacity, not a headline estimate
Before a standard-cell library is fully characterized, any single claim such as “X gates per square millimetre” would create false precision.
Cell dimensions, routing rules, process corners and usable die architecture all matter.
As the platform matures, xSilica will publish practical reference circuits, characterized cell data and example layouts. That will make it possible to answer the capacity question in the way engineers actually need it answered:
Show me what functions have been built, how large they were, and what the silicon did.
References
[1] M. Khazraee, L. Zhang, L. Vega, and M. B. Taylor, “Moonwalk: NRE Optimization in ASIC Clouds,” in Proc. 22nd ACM Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS), Xi'an, China, 2017, pp. 511–526, doi: 10.1145/3037697.3037749. [Online]. Available: https://michaeltaylor.org/papers/Khazraee_ASIC_Cloud_NRE_ASPLOS_2017_final.pdf.
[2] imec, “Innovate with hardware in today’s substream markets,” Dec. 23, 2016. [Online]. Available: https://www.imec-int.com/en/articles/the-new-hardware-hipsters. [Accessed: Sep. 8, 2026].